Abstrac:

With the end of lithography scaling [1] as a key driver for technology improvement and the end of Dennard scaling [2], improvements in application performance will increasingly come from customized memory hierarchies and accelerator devices. The form of the memory hierarchies and type of accelerators have been the focus of much research, but I contend that it doesn’t matter. The lessons of the past, in particular the IBM Cell accelerators and the GPGPU revolution, have taught us that focusing on one particular accelerator system comes with implicit disruption: software is often no longer portable. With new accelerator architectures coming online (including Non-von Neumann ones) and increasing willingness from vendors to package accelerators using chiplet-like technology [3], the number of accelerators will likely increase as will the frequency of disruption within the software ecosystem unless we as a community to disrupt the disruption. The key challenge for all future systems is how to balance two juxtaposed needs: to minimize disruption in architecture (as opposed to micro-architecture) while minimizing the disruption to the entire software stack (firmware/operating system/runtime/user-space applications). The question is, how do we shape future interfaces as a hardware/software co-design process to enable us to ease disruption as we step bravely into our post-Moore future?

Talk Outline:

• Key grand challenges from a hardware/software perspective (high level)
• Why it matters, key examples of how disruption and “progress” in the underlying hardware leads to lasting disruption in the entire software stack.
• Brief overview of where disruption could come from, pull in slides and data from previous ASCAS reports, DoE workshops, and my own work. This includes both:
• Heterogeneous memory technology, interface
• Storage
• Accelerators
• Specific target surfaces, hot-spots, facing disruption:
• Use genome example where some regions are evolutionarily stable and others face massive drift under selective pressure
• Tie in language and programming models to this surface
• What language and runtime designers are doing to minimize disruption and what we’re accidentally doing to make it worse. Will show specific examples.
• What can we do as software engineers to prepare for tomorrow’s new architectures to disrupt disruption.
• How we can look forward to, and stop worrying about our non-von Neumann future

References:

1. Fuller, G. (2017, August). Future lithography technology. In Single Frequency Semiconductor Lasers (Vol. 10321, p. 1032105). International Society for Optics and Photonics.
2. Henkel, J., & Montuschi, P. (2017). Computer Engineers' Challenges for the Next Decade: The Triangle of Power Density, Circuit Degradation, and Reliability. Computer, 50(7), 12-12.
3. Rigo, A., Pinto, C., Pouget, K., Raho, D., Dutoit, D., Martinez, P. Y., ... & Bartsch, V. (2017, August). Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach. In Digital System Design (DSD), 2017 Euromicro Conference on (pp. 486-493). IEEE.